1. Field of the Invention
The present invention generally relates to the field of information technology and, more particularly, to a sharing buffer management method and system.
2. Description of Related Art
Researchers have proposed hardware-based transactional memory systems to ameliorate problems existing in traditional lock-based parallel programming models. Transactional memory systems allow programmers to specify regions of code called transactions that execute in a serialized fashion. That is to say, each transaction only executes its corresponding code in a thread. Transactional memory systems allow applications to access shared data in a parallel and atomic fashion.
Transactional memory can improve the performance of parallel programs. The article “Transactional Memory: Architectural Support for Lock-Free Data Structures,” by M. P. Herlihy and J. E. B. Moss, in Proceedings of the 1993 International Symposium on Computer Architecture (ISCA), May 1993, San Diego, Calif., contains information on the implementation of transactional memory and some related terms or concepts. Hardware dedicated buffers and related control mechanisms are widely adopted in hardware or hybrid transactional memory systems to implement version management and conflict detection.
The design of hardware dedicated buffers is closely related with the features of multi-core architecture. There are two important features or trends observed from the development of multi-core architecture. The simultaneous multi-threading (SMT) processor core is becoming more and more popular. Also, more cores are integrated in the same chip. High implementation costs will result if each hardware thread, in case of a SMT core, or each core, in the case of a multi-core system, needs a private dedicated buffer. Therefore, it is necessary to share the buffer among multiple hardware threads for a SMT core or processor cores for a multi-core system.
Traditional management methods for a hardware sharing buffer can be generally categorized by two different approaches.
(1) Exclusive Sharing Buffer
All the transactions from different threads contend for the same sharing buffer, and only one transaction can be allowed to access this sharing buffer, i.e., exclusive access, until the whole transaction finishes as a result of successful commit or retry. Therefore, an exclusive sharing buffer can be implemented with simple hardware logic. However, such a design possibly leads to performance loss, since it greatly limits potential concurrency.
(2) Non-Exclusive Sharing Buffer
In this design, data from different transactions is marked with different colors. The transactions are distributed in the sharing buffer. Such distribution is usually carried out at the fine granularity of cache line unit. In order to tell the transaction which data is stored in each cache line, each cache line in a buffer has a corresponding color mark. The major advantage of a non-exclusive sharing buffer is that it can get better resource utilization when compared with exclusive sharing methods.
However, the design for a non-exclusive sharing buffer will significantly increase the implementation complexity of transaction commit, abort, replacement, as well as conflict detection. In this case transactions are randomly distributed in the non-exclusive sharing buffer at traditional fine granularity, i.e., at the granularity of the cache line.
For transaction commit and transaction abort, hardware logic has to compare each cache line to match the target color; for replacement policy in case of conflict miss, it is hard for hardware to choose one transaction to be replaced, for example, a small transaction might abort a large one, or a new transaction might abort one which is to be committed; and for conflict detection, hardware has to attach a color register and corresponding comparison logic for each cache line. This significantly increases the hardware cost.